The present invention relates to semiconductor devices and the fabrication thereof. More particularly, the present invention pertains to rough conductive layers of ruthenium and/or ruthenium oxide.
In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers of contact holes, vias, etc.
As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material.
Further, to the increase the capacitance for a storage cell capacitor of a memory device without increasing the occupation area of the storage cell capacitor, various techniques have been used to increase the surface area of the lower electrode of the capacitor. For example, hemispherical grains (HSG) have been used to enhance such surface area of the lower electrode of a capacitor of a memory device.
In one illustrative HSG technique, an HSG silicon surface is used as an underlayer for a metal layer to form a lower electrode having an increased surface area. For example, such a coextensive conductive layer formed over the hemispherical grain silicon surface may be formed of titanium nitride.
However, in many cases, the use of HSG to enhance surface area of the lower electrode is problematic. For example, when an HSG silicon surface is used as an underlayer for a metal in a container capacitor (e.g., a container capacitor such as described in U.S. Pat. No. 5,270,241 to Dennison, et al., entitled xe2x80x9cOptimized Container Stack Capacitor DRAM Cell Utilizing Sacrificial Oxide Deposition and Chemical Mechanical Polishing,xe2x80x9d issued Dec. 14, 1993) there is a possibility of forming silicon dioxide between the HSG silicon surface and the metal layer of which the electrode is formed when the dielectric layer is being formed due to the diffusion of oxygen through the metal layer. Further, there is the possibility of silicon dioxide formation between the metal layer and the dielectric being formed due to the diffusion of silicon through the metal layer. Such silicon dioxide formation is likely due to the oxygen anneal required for formation of high dielectric constant materials, e.g., Ta2O5 or BaSrTiO3, over the lower electrode.
However, reliable electrode connections are necessary. Formation of silicon dioxide as described above decreases the reliability of the electrode connection. Further, such silicon dioxide formation may result in a decreased series capacitance, thus degrading the storage capacity of the cell capacitor.
To prevent the diffusion of oxygen to the HSG silicon surface, or the diffusion of silicon through the metal layer, the use of a diffusion barrier, such as titanium nitride, may be used between the HSG silicon surface to form the lower electrode. The use of a diffusion barrier over the HSG silicon surface, however, also has problems associated therewith. For example, the container size of a container capacitor is relatively small. With use of multiple layers, such as HSG silicon surface, a diffusion barrier, and then a lower metal electrode layer, a container having an undesirably large size may be required.
Further, formation of a diffusion barrier layer over an increased surface area of an HSG silicon surface, and thereafter a lower metal electrode layer thereon, will decrease the effectiveness of the HSG layer to increase the surface area of the lower electrode. In other words, the surface area of the HSG silicon surface is decreased by application of the diffusion barrier layer, and then further decreased by the application of the lower electrode layer. In such a manner, the effectiveness of increasing the lower electrode surface area with use of HSG is diminished.
Further, grain size of an HSG silicon surface is somewhat limited. For example, such grain size is typically less than 200 xc3x85 in nominal diameter. As such, the increase in surface area provided through use of HSG is limited accordingly.
Generally, various metals and metallic compounds, for example, metals such as ruthenium and platinum, and conductive metal oxides, such as ruthenium oxide, have been proposed as the electrodes for at least one of the layers of an electrode stack for use with high dielectric constant materials. Ruthenium oxide and ruthenium electrodes have been employed as electrode materials because of the ability to easily etch such materials. For example, the article entitled, xe2x80x9c(Ba,Sr)TiO3 Films Prepared by Liquid Source Chemical Vapor Deposition on Ru Electrodes,xe2x80x9d by Kawahara et al., Jpn. J. Appl. Phys., Vol. 35 (1996), Part 1, No. 9B (September 1996), pp. 4880-4885, describes the use of ruthenium and ruthenium oxide for forming electrodes in conjunction with high dielectric constant materials. As described therein, surface roughening of such materials is believed to attribute to degradation of the structures being formed.
Further, as described therein, ruthenium and ruthenium oxide materials were deposited by physical vapor deposition (PVD) processing, e.g., reactive RF sputtering processes. Many storage cell capacitors are fabricated which include electrode layers that are formed of a conductive material within a small high aspect ratio opening. Typically, sputtering does not provide a sufficiently conformal layer adequate for formation of an electrode layer within such a small high aspect ratio opening.
There is a need in the art to increase the surface area of a lower electrode structure without increasing the occupation area of the capacitor structure. Further, it is desirable that such an increase in surface area does not have one or more of the problems described above associated with the use of HSG. To overcome the problems described above, and others that will be readily apparent from the description below, rough conductive layers of ruthenium and/or ruthenium oxide are formed according to the present invention. For example, a rough conductive layer including ruthenium can be used as the lower or bottom electrode of a capacitor structure increasing the surface area of the lower electrode without increasing the occupation area and without the need for HSG silicon formation. As HSG silicon is not used, there is less danger of silicon dioxide formation. Further, the use of a rough conductive layer of ruthenium and/or ruthenium oxide may reduce processing costs by eliminating the need for HSG silicon formation and possibly formation of a diffusion barrier.
A method for forming a rough conductive layer (e.g., a layer having an RMS surface roughness in a range of about 50 xc3x85 to about 600 xc3x85) in the fabrication of integrated circuits according to the present invention includes providing a substrate assembly in a reaction chamber with the substrate assembly including a surface. The substrate assembly surface is maintained at a temperature in a range of about 100xc2x0 C. to about 400xc2x0 C. and the pressure of the reaction chamber is maintained in a range of about 0.4 torr to about 10 torr. A carrier gas at a flow rate of about 100 sccm to about 500 sccm is provided through a ruthenium-containing precursor maintained at a temperature of about 15xc2x0 C. to about 100xc2x0 C. into the reaction chamber to deposit a rough ruthenium layer on the surface of the substrate assembly.
In various embodiments of the method, the method may include providing a diluent gas at a flow rate of about 100 sccm to about 500 sccm into the reaction chamber, the substrate assembly surface may be maintained at a temperature in the range of about 150xc2x0 C. to about 250xc2x0 C., the rough ruthenium layer may be deposited at a rate of about 100 xc3x85/minute to about 500 xc3x85/minute, and the method may further include annealing the rough ruthenium layer at a temperature in a range of about 300xc2x0 C. to about 900xc2x0 C. for a time period in a range of about 30 seconds to about 30 minutes. Further, the anneal may be performed in a gas atmosphere subjected to a glow discharge created by applying an electromagnetic field across the gas mixture.
In another method according to the present invention for forming a rough conductive layer in the fabrication of integrated circuits, a substrate assembly including a surface is provided in a reaction chamber. A ruthenium-containing precursor is provided into the reaction chamber and a rough ruthenium layer is deposited on the surface of the substrate assembly at a rate of about 100 xc3x85/minute to about 500 xc3x85/minute, preferably at a rate of about 200 xc3x85/minute to about 300 xc3x85/minute.
Another method for forming a rough conductive layer (e.g., a layer having an RMS surface roughness in a range of about 50 xc3x85 to about 600 xc3x85) in the fabrication of integrated circuits according to the present invention includes providing a substrate assembly having a surface into a reaction chamber. A ruthenium-containing precursor is provided into the reaction chamber along with an oxygen-containing precursor. A rough ruthenium oxide layer is deposited on the surface of the substrate assembly at a rate of about 100 xc3x85/minute to about 1200 xc3x85/minute, preferably, at a rate of about 300 xc3x85/minute to about 600 xc3x85/minute.
In one embodiment of the method, the ruthenium-containing precursor is provided into the reaction chamber by providing a carrier gas at a flow rate of about 100 sccm to about 500 sccm through the ruthenium-containing precursor maintained at a temperature of about 15xc2x0 C. to about 100xc2x0 C., and then into the reaction chamber. Further, the oxygen-containing precursor is provided into the reaction chamber at a flow rate of about 100 sccm to about 2000 sccm.
In other embodiments of the method, the substrate assembly surface may be maintained at a temperature in a range of about 100xc2x0 C. to about 400xc2x0 C., the pressure of the reaction chamber may be maintained in a range of about 0.4 torr to about 100 torr, and the rough ruthenium oxide layer may be annealed at a temperature in a range of about 300xc2x0 C. to about 900xc2x0 C. for a time period in a range of about 30 seconds to about 30 minutes. Further, the anneal may be done in a gas atmosphere subjected to a glow discharge created by applying an electromagnetic field across the gas mixture.
A conductive structure according to the present invention includes at least a rough ruthenium layer. A surface of the rough ruthenium layer has a surface area greater than about 1.2 times a surface area of a completely smooth surface having a substantially identical shape as the surface of the rough ruthenium layer. Preferably, the surface area is greater than about 1.5 times the surface area of the completely smooth surface having the substantially identical shape as the surface of the rough ruthenium layer.
In other embodiments of the conductive structure, the conductive structure may include non-rough ruthenium upon which the rough ruthenium is formed. Likewise, the conductive structure may include non-rough ruthenium oxide upon which the rough ruthenium is formed.
Another conductive structure according to the present invention includes at least a rough ruthenium oxide layer. A surface of the rough ruthenium oxide layer has a surface area greater than about 1.2 times a surface area of a completely smooth surface having a substantially identical shape as the surface of the rough ruthenium oxide layer. Preferably, the surface area is greater than about 1.5 times the surface area of the completely smooth surface having the substantially identical shape as the surface of the rough ruthenium oxide layer.
In other embodiments of the conductive structure, the conductive structure may include non-rough ruthenium upon which the rough ruthenium oxide is formed.
In other embodiments of the present invention, the above methods and conductive structures may be formed as part of a capacitor structure. For example, the conductive structure may be formed as a first electrode or bottom electrode of a capacitor.